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data sheet ics841664agi revision a august 10, 2011 1 ?2011 integrated device technology, inc. femtoclock ? crystal-to-hcsl clock generator ics841664i 0 1 1 0 na nb osc femtoclock pll vco = 625 mhz m = 25 fref xtal_in 25mhz xtal_out ref_in ref_sel iref bypass fsel[0:1] mr/noe nref_oe qb 0 nqb0 qb 1 nqb1 qa0 nqa0 qa 1 nqa1 ref_out pulldown pulldown pulldown pulldown pulldown pullup 1 2 3 4 5 6 7 nref_oe ref_out gnd bypass 8 9 10 11 12 13 14 qa v dda v dd nqa gnd qa ref_in v ddoa ref_ sel xtal _in xtal_out 28 27 26 25 24 23 22 21 20 19 18 17 16 15 iref fsel qb gnd mr/noe fsel nqb v ddob v dd gnd 1 nqa1 qb1 nqb1 00 0 0 0 1 general description the ics841664i is an optimized srio clock generator and a member of the family of high-performance clock solutions from idt. the device uses a 25mhz parallel crystal to generate 125mhz and 156.25mhz clock signals, replacing solution requiring multiple oscillator and fanout buffer solutions. the device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter srio clock signals. designed for telecom, networking and industrial application, the ics841664i can also drive the high-speed srio serdes clock inputs of communication processors, dsps, switches and bridges. features ? four differential hcsl clock outputs: configurable for srio (125mhz or 156.25mhz) clock signals one ref_out lvcmos/lvttl clock output selectable crystal oscillator interface, 25mhz, 18pf parallel resonant crystal or lvcmos/lvttl single-ended reference clock input or lvcmos/lvttl single-ended input supports the following output frequencies: 125mhz or 156.25mhz vco: 625mhz supports pll bypass and output enable functions rms phase jitter, using a 25mhz crystal (1.875mhz - 20mhz): 0.45ps (typical) @ 125mhz full 3.3v power supply mode -40c to 85c ambient operating temperature available in lead-free (rohs 6) package ics841664i 28-lead tssop 6.1mm x 9.7mm x 0.925mm package body g package top view pin assignment block diagram
ics841664agi revision a august 10, 2011 2 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics , for typical values. table 2. pin characteristics number name type description 1, 18 v dd power core supply pins. 2 ref_out output lvcmos/lvttl reference frequency clock output. 3, 7, 15, 22 gnd power power supply ground. 4, 5, 8, 9 qa0, nqa0 qa1, nqa1 output differential bank a output pairs. hcsl interface levels. 6v ddoa power output supply pin for bank a outputs. 10 nref_oe input pullup active low ref_out enable/disable. see table 3e. lvcmos/lvttl interface levels. 11 bypass input pulldown selects pll/pll bypass mode. see table 3c. lvcmos/lvttl interface levels. 12 ref_in input pulldown lvcmos/lvttl reference clock input. 13 ref_sel input pulldown reference select, selects the input reference source. see table 3b. lvcmos/lvttl interface levels 14 v dda power analog supply pin. 16,17 xtal_out, xtal_in input parallel resonant crystal interface. xtal_out is the output, xtal_in is the input. 19 mr/noe input pulldown active high master reset. active low output enable. when logic high, the internal dividers are reset and the outputs are in high impedance (hiz). when logic low, the internal dividers and the outputs are enabled. see table 3d. lvcmos/lvttl interface levels. 20, 21, 24, 25 nqb0, qb0 nqb1, qb1 output differential bank b output pairs. hcsl interface levels. 23 v ddob power output supply pin for bank b outputs. 26, 27 fsel1, fsel0 input pulldown output frequency select pins. lvcmos/lvttl interface levels. 28 iref output hcsl current reference resistor output. a fixed precision resistor (475 ? ) form this pin to ground provides a reference current used for differential current-mode qxx/nqxx clock outputs. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf c pd power dissipat ion capacitance v dd = 3.465v 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance ref_out v dd = 3.465v 20 ?
ics841664agi revision a august 10, 2011 3 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator function tables table 3a. na, nb fselx function table (f ref = 25mhz) table 3b. ref_sel function table table 3c. bypass function table note 1: asynchronous control. table 3d. mr/noe function table note 1: asynchronous control. table 3e. nref_oe function table note 1: asynchronous control. inputs outputs frequency settings fsel1 fsel0 m qa0:1/nqa0:1 qb0:1/nqb0:1 0 0 25 vco/5 (125mhz) vco/5 (125mhz) 0 1 25 vco/5 (125mhz) vco/4 (156.25mhz) 1 0 25 vco/5 (125mhz) qb0:1 = l, nqb0:1 = h 1 1 25 vco/4 (156.25mhz) vco/4 (156.25mhz) input ref_sel input reference 0xtal 1ref_in input bypass pll configuration note 1 0 pll enabled 1 pll bypassed (qa, qb = fref/nx, x = a or b) input mr/noe function note 1 0 outputs enabled 1 internal dividers reset, outputs disabled (high impedance) input nref_oe function note 1 0 ref_out enabled 1 ref_out disabled (high impedance)
ics841664agi revision a august 10, 2011 4 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddoa = v ddob = 3.3v5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v5%, t a = -40c to 85c note 1: outputs termination with 50 ? to v dd /2. see parameter measurement information section, output load test circuit diagram. item rating supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to v dd -0.5v to v dd + 0.5v outputs,i o continuous current ref_out surge current ref_out +/- 15ma +/- 30ma package thermal impedance, ja 64.5 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.20 3.3 3.465 v v ddoa, v ddob output supply voltage 3.135 3.3 3.465 v i dd power supply current no load 80 ma i dda analog supply current no load 20 ma i ddoa, i ddob output supply current no load, rref = 475 ? +/? 1 %5ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current ref_in, ref_sel, bypass, mr/noe, fsel0, fsel1 v dd = v in = 3.465v 150 a nref_oe v dd = v in = 3.465v 5 a i il input low current ref_in, ref_sel, bypass, mr/noe, fsel0, fsel1 v dd = 3.465v, v in = 0v -5 a nref_oe v dd = 3.465v, v in = 0v -150 a v oh output high voltage; note 1 ref_out v dd = 3.465v 2.6 v v ol output low voltage; note 1 ref_out v dd = 3.465v 0.5 v
ics841664agi revision a august 10, 2011 5 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. ac electrical characteristics table 6a. lvcmos ac characteristics, v dd = 3.3v5%, t a = -40c to 85c parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf symbol parameter test conditions minimum typical maximum units f out output frequency ref_out 25 mhz t r / t f output rise/fall time 20% to 80% 1.5 2.2 ns odc output duty cycle 47 53 %
ics841664agi revision a august 10, 2011 6 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator table 6b. hcsl ac characteristics, v dd = v ddoa = v ddob = 3.3v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all measurements are taken at 125mhz and 156.25mhz. note 1: please refer to the phase noise plot. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f out output frequency vco/5 125 mhz vco/4 156.25 mhz t jit(?) rms phase jitter (random); note 1 125mhz, integration range: 1.875mhz - 20mhz 0.45 0.55 ps 156.25mhz, integration range: 1.875mhz - 20mhz 0.41 0.54 ps t jit(cc) cycle-to-cycle jitter; note 3 60 ps t sk(o) output skew; note 2, 3 qax/nqax, qbx/nqbx 140 ps t l pll lock time 100 ms v high voltage high 650 700 950 mv v low voltage low -150 150 mv v ovs max. voltage, overshoot 0.3 v v uds min. voltage, undershoot -0.3 v v rb ringback voltage 0.2 v v cross absolute crossing voltage 200 550 mv ? v cross total variation of v cross over all edges 160 mv t r / t f output rise/fall time qax/nqax, qbx/nqbx measured between 0.175v to 0.525v 100 700 ps ? t r / ? t f rise/fall time variation 125 ps odc output duty cycle qax/nqax, qbx/nqbx 47 53 %
ics841664agi revision a august 10, 2011 7 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator typical phase noise at 125mhz at 3.3v typical phase noise at 156.25mhz at 3.3v noise power dbc hz offset frequency (hz) 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.45ps typical) noise power dbc hz offset frequency (hz) 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.41ps typical
ics841664agi revision a august 10, 2011 8 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator parameter measurement information 3.3v hcsl output load ac test circuit 3.3v lvcmos output load ac test circuit cycle-to-cycle jitter 3.3v hcsl output load ac test circuit rms phase jitter hcsl output skew 475 ? 50 ? 50 ? gnd 0v scope iref 0v 3.3v5% v dd , v ddoa v ddob v dda 3.3v5% scope qx gnd v dd v dda 1.65v5% 1.65v5% -1.65v5% lv c m o s nqa[0:1], qa[0:1], ? ? ? ? t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nqb[0:1] qb[0:1] 475 ? measurement point 33 ? 50 ? 50 ? 33 ? measurement point 49.9 ? 49.9 ? hcsl gnd 2pf 2pf 0v iref 3.3v5% 3.3v5% v dd , v ddoa v ddob v dda qx nqx offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power nqx qx nqy qy t sk(o)
ics841664agi revision a august 10, 2011 9 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator parameter measurement information, continued lvcmos output rise/fall time differential measurement points for rise/fall time se measurement points for delta cross point lvcmos output duty cycle/pulse width/period differential measurement points for duty cycle/period differential measurement points for ringback 20% 80% 80% 20% t r t f ref_out nqax, 0.175v 0.525v 0.525v 0.175v t r t f v sw i n g nqbx qax, qbx ? v cross nq q _delta= 140mv qx nqx t period t pw t period odc = v dd 2 v dd 2 x 100% t pw ref_out q - nq 0.0v clock period (differential) positive duty cycle (differential) negative duty cycle (differential) t stable v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v v rb t stable
ics841664agi revision a august 10, 2011 10 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator parameter measurement information, continued se measurement points for absolute cross point/swing applications information recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. ref_clk input for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. lvcmos control pins all control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: hcsl outputs all unused hcsl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvcmos outputs all unused lvcmos outputs can be left floating. there should be no trace attached. v cross_max v cross_min v max v min nq q = -0.30v
ics841664agi revision a august 10, 2011 11 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator applications information, continued schematic layout figure 1 shows an example of ics841664i application schematic. in this example, the device is operated at v dd = v dda = v ddoa = v ddob = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the load capacitance c1 = 27pf and c2 = 27pf are recommended for frequency accuracy. depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specifications can be used. this will require adjusting c1 and c2. for this device, the crystal load capacitors are required for proper operation. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ics841664i provides separate power supplies to isolate any high switching noise from coupling into the internal pll. figure 1. ics841664i schematic example in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1f capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequency. this low-pass filter starts to attenuate noise at approximately 10 khz. if a specific frequency noise component with high amplitude interference is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally general design practice for power plane voltage stability suggests adding bulk capacitances in the general area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. vd d ref _i n zo = 50 hcsl termination fs el1 c12 0.1uf re f _o u t vd d a mr/ noe r3 33 vdd nqb 1 r5 50 zo = 50 set logic input to '0' nq b 0 vd d r4 33 vddob=3.3v qb1 r1 0 50 + - nref_oe ru 2 no t i ns t all r8 0-33 c10 10uf zo = 50 ohm vddoa=3.3v hcsl optional termination rd 2 1k zo = 50 ro ~ 7 o hm q1 dr iv e r_ l vc mo s logic control input examples bl m18 bb2 2 1sn 2 f e r ri t e b e ad 1 2 c1 27 p f c8 0.1uf (u 1 :6 ) r9 0-33 r6 50 c1 1 0. 1u f zo = 50 (u1:23) vd d fs el0 vd d o c7 0. 1 uf c9 0.1uf 3. 3 v r1 33 + - optional set logic input to '1' 3. 3 v to l ogi c input pins x1 25mhz b lm18bb221s n1 ferrite bead 1 2 vdd c4 10 u r1 1 50 vdd=3.3v to logic input pins r12 43 r7 10 lvcmos c3 0.1u 18pf ref_sel recommended for pci express point-to-point connection zo = 50 c6 10uf vd d (u1:18) rd 1 no t i ns t all vd d o u1 1 2 3 4 5 14 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 12 13 28 27 26 25 vdd ref _o u t gn d qa 0 nq a 0 vdd a vdd o a gn d qa 1 nq a 1 nr e f _ o e byp ass gn d xtal_ou t xt a l _i n vd d mr/noe nqb1 qb1 gn d vd d ob nqb0 ref _i n ref _se l iref fsel0 fsel1 qb0 c2 27pf r2 47 5 (u 1 :1 ) vdd c5 0.1uf recommended for pci express add-in card ru 1 1k by pa ss vd d o qb 0
ics841664agi revision a august 10, 2011 12 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator applications information, continued overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 2a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 2b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpecl driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xtal_out xtal_in zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ics841664agi revision a august 10, 2011 13 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator applications information, continued recommended termination figure 3a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3a. recommended source termination (where the driver and receiver will be on separate pcbs) figure 3b is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
ics841664agi revision a august 10, 2011 14 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator power considerations this section provides information on power dissipation and junction temperature for the ics841664i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics841664i is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. core and hcsl output power dissipation power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (80ma + 20ma) = 346.5mw power (outputs) max = 44.5mw/loaded output pair if all outputs are loaded, the total power is 4 * 44.5mw = 178mw lvcmos driver power dissipation dynamic power dissipation at 25mhz power (25mhz) = c pd * frequency * (v dd ) 2 = 4pf * 25mhz * (3.465v) 2 = 1.20mw per output total power dissipation total powe r = power (core) + power (outputs) + total power (25mhz) = 346.5mw + 178mw + 1.2mw = 525.7mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 64.5c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.526w * 64.3c/w = 118.9c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 28 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 64.5c/w 60.4c/w 58.5c/w
ics841664agi revision a august 10, 2011 15 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 4. figure 4. hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out since v out = i out * r l power = (v dd_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 44.5mw v dd v out r l 50 ? ic ? i out = 17ma r ref = 475 ? 1%
ics841664agi revision a august 10, 2011 16 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator reliability information table 8. ja vs. air flow table for a 28 lead tssop transistor count the transistor count for ics841664i is: 2954 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 64.5c/w 60.4c/w 58.5c/w
ics841664agi revision a august 10, 2011 17 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator package outline and package dimensions package outline - g suffix for 28 lead tssop table 9. package dimensions reference document: jedec publication 95, mo-153 all dimensions in millimeters symbol minimum maximum n 28 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 9.60 9.80 e 8.10 basic e1 6.00 6.20 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics841664agi revision a august 10, 2011 18 ?2011 integrated device technology, inc. ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 841664agilf ics841664agi 28 lead ?lead-free? tssop tube -40 c to 85 c 841664agilft ics841664agi 28 lead ?lead-free? tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial and industrial applications. any other applications, such as those requiring high reliability or othe r extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics841664i data sheet femtoclock ? crystal-to-hcsl clock generator disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of any kind, whether e xpress or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an imp lied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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